The ceramic materials listed are manufactured in plate form for use in the fabrication of single layer capacitors, custom build to print products [parts designed by customers and manufactured using DLI thin film processes] and DLI designed thin film products. DLI originated thin film designs are only implemented using PI, PG, CF, and CG materials. SLC’s may utilize any of the materials. PI, QZ, and AG are purchased from outside sources.

Class I Dielectric Materials -  Thin Film Products

 

 

CHOOSING THE METAL SYSTEM

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The choice of a metal system is governed by one or more of the following features.

• Filter mounting technique - solder - surface mount,
• Filter mounting technique - conductive epoxy mount,
• Vias and/or Castellations
• Insertion loss – conductor thickness, frequency of operation and skin depth.
• Line width and line spacing requirements.
• The requirement for integrated resistors.
• The current carrying requirements.

 

Basic Metals and Thin Film Circuit Function

 

 

Metallization Systems, Application, and Physical Parameters

 

Metallization Systems

Conductor Sheet Resistivity

Sheet resistivity is typically 30 % higher with plated metal as compared to bulk resistivity of the same material and 20% higher with sputtered metal. See appendix for industry resistivity values.

Skin Depth

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The metallization layers and thickness is governed by the mounting strategy (ceramic circuit to next level part), insertion loss and current carrying requirements, the chip/component attachment process, and the input/output connections. The requirement for resistors will necessitate a metallization system that starts with an adhesion layer of tantalum nitride (TaN). Wirebonding to the gold (Au) surface of a circuit generally requires a minimum of 50 µ” of gold, although 100 µ” is recommended for most applications. When tin/lead soldering will be employed, a solderable barrier like nickel is required and the outer gold layer is used to prevent nickel oxidation and the thickness is minimized [5 to 20 µ”] to reduce solder embrittlement.

 

Gold-Tin Solder Offering

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Gold-tin solder systems are employed in hybrid microelectronic applications for the mounting of semiconductor die to the parent circuit. Gold tin solder may be sputtered in selected areas of a circuit to facilitate component attachment. For areas within the substrate perimeter allow a 0.003 inch (0.076 mm) clearance to the border of the conductor to accommodate processing variation. This allowance is not required at the substrate edge.


Caution must be observed when exposing gold plated circuits to the elevated temperatures required to perform component attachment using solder. Prolonged exposure to elevated temperatures is sufficient to drive the underlying Ni barrier layer up through the gold, rendering the surface unbondable. Observe maximum temperatures listed in the tables. At 425 oC nickel can diffuse through 150 Microinches of gold in 15 minutes.

Also, surface concentrations of carbon on the gold surface can exceed 60% after the circuit has been put through a soldering operation. The maximum time at temperature and the duration have an impact on the ability to achieve acceptable wirebonds. It is recommended that plasma cleaning be employed prior to wirebonding.

 

FINE LINE CONDUCTOR FEATURES

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The key to superior and repeatable performance in microwave structures is the control of the critical geometries of the metal features. Devices such as filters, diplexers, Lange couplers, directional couplers, interdigitated capacitors, and spiral inductors rely on the precision of the conductor line width and line spacing to achieve performance. The characteristic impedance of transmission lines is also governed by line widths. The coupling between transmission lines and the control of the even and odd mode impedance, to implement couplers and filters is governed by the line widths and the spacing between the adjacent transmission lines. The precise control of the spacing between the coupled lines ensures uniformity in VSWR and coupling necessary to make coupler and filter performance repeatable.

 

Metal Layer	With Vias – Minimum Line Width/Spacing	Without Vias – Minimum Line Width/Spacing
Au ( 10 to 150 µ”) (sputtered)	1.0	0.8
Au (150 to 300 µ”) (sputtered)	1.5	1.0
Au (300 to 850 µ”) (sputtered)	3.0	3.0
Cu ( 50 to 600 µ”) (sputtered)	3.0	3.0
Cu (0.5 to 6 mils; Plated)	3.0	3.0
NiV ( 50 to 125 µ”) (sputtered)	3.0	3.0

 

With the selection of the proper substrate/ metallization system, excellent edge acuity can be achieved. The edge acuity is dependent on the thickness of the metal layers required, but generally is less than 0.1 mil.

Finished line widths will be within +/- 0.1 mils of the design dimension.

Fine line width and line space geometries are impacted by the quality of the ceramic surface. Some materials used in thin film products have grain structures and surface imperfections that may cause the loss of control of fine line widths and line space geometries. Polishing, which improves the quality of the surface, is also somewhat limited in that some materials do not hold up well to the forces created during polishing.

One material that is not as limited is polished alumina. The surface quality is good and 1 mil line width/spacing is possible and repeatable when vias are present and 0.75 mil line width/spacing is possible and repeatable when vias are not used.
 

 

VIA DESIGN

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There are three distinct ways to plate the via:

• Standard Via
• Reinforced Via
• Filled Via

 

Plated Via Holes – Standard and Reinforced

The application of plated via’s allows the design engineer to connect the circuit to the ground-plane.
 

 

Most applications which use plated via’s find standard metal thickness through the holes acceptable. If higher currents are required, consider reinforcing the plated via. This may also be necessary to reduce RF loss in devices such as interdigital band pass filters.

This is done through a separate (additional processing) plating step in which DLI adds additional metal in and around the via to give better mechanical strength and lower via hole resistance. Refer to “Selective Plating Strategies” below.

 

 

Via Dimension

 

 

Via Proximity

 

Filled Vias

Filled via’s provide a good thermal path and ground return path from the top side conductors to the backside ground plane. In the case of mounting active die, the use of an array of filled via’s effectively shunts heat away from the die. However, the technology is difficult to implement without issue and suffers from a significant processing cost penalty. When necessary, use gold fill for the via. Copper or silver filled via’s can leach into other components of the metallization system, thereby leading to reliability problems.

CTE mismatch between the ceramic and the metal in the via may create cracking issues.

Filled vias are not recommended for use unless a customer specifically requires the technology.

 

 

Via Taper

Laser drilling of via’s will produce a taper from the entrance to the exit of the via hole.

 

 

 

Selective Plating Strategies

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Selective plating is the application of different metal systems in different areas of a circuit or an additional plate up of the same metal in selected areas. Examples are the addition of a nickel metal layer in area where solder is required or to increase the metal thickness in vias or castellation walls without using nickel on the resonators of filters. Added metal, nickel, would be necessary in the I/O castellations and on the ground plane side of a filters for solder attach.

Many customers will only require 50 µ” of nickel and 3-6 µ” of gold. This 3-6 µ” of Au comes from the fact that this is the maximum thickness of gold that can be electrolessly plated. During electroless gold plating, the gold ions attach to the surface of the nickel, but the chemical process stops once the nickel surface is completely covered (the gold will not continue to plate onto itself). The disadvantage to this process is that the plated gold thickness is restricted. However, the significant advantage of electroless plating over electrolytic plating is that the plating does not require an electrical charge to be flowing through the surfaces that need to be plated. I.e. isolated features will get plated.

Electrolytic plating has one major disadvantage. Electrolytic plating requires an electrical current to be flowing through the surfaces that need to be plated. This means that the plated surfaces need to have electrical continuity to the edges of the plate, since that’s where the electrical terminals are attached during the process. Although, electrical continuity is typically not an issue for thin film filter designs. The major design advantage of electrolytic plating is that the plated gold thickness can exceed 3-6 µ”, since gold can continuously plate onto itself as long as an electrical current is flowing through it and attracting the gold cations to the surface. These thicker gold plating schemes are required by some customers.
 

RESISTOR DESIGN GUIDELINES

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DLI employs tantalum nitride (TaN) in the implementation of resistors This material has become the more widely accepted resistor material because of the higher maximum exposure temperature, the wider annealing window, and the superior resistance to harsh environments encountered in soldering and other processing.

The key design parameters that the engineer needs to be concerned with are: the resistor value, the stability with time and temperature, and power handling. The design of a thin film resistor is governed by the following equation:

R = L/Wt

Where:
R = Total Resistance ()
 = Bulk Resistivity of Resistor Material (-cm)
L = Resistor Length (cm)
W = Resistor Width (cm)
t = Resistor Thickness (cm)

To ease design, a parameter known as sheet resistivity is provided. This term assumes L = W in the above equation so that:
Rsheet = RS = /t (/square). Therefore simply multiplying RS by the Length (L) divided by the width (W) yields the actual resistance. RTotal = Rsheet x Length (L)/Width (W)

The resist metallization layer for all the resistors on a given circuit is deposited in a single sputter operation. Thus, resistors on a single part must share the same resistivity. DLI typically uses 50  per square for most work. Refer to the Standard Resistor Parameters table for electrical design parameters and allowable limits.
 

 

There are two fundamental resistor layout techniques, the notched resistor implementation and the flush resistor process.

The flush resistor is preferred due to ease of manufacturing and more consistent results.

Resistor Layout Guides